RESEARCH

Power Semiconductor Device

A power semiconductor device is a semiconductor device used as a switch or rectifier in power electronics (for example in a switch-mode power supply). Such a device is also called a power device or, when used in an integrated circuit, a power IC. A power semiconductor device is usually used in "commutation mode" (i.e., it is either on or off), and therefore has a design optimized for such usage; it should usually not be used in linear operation. Linear power circuits are widespread as voltage regulators, audio amplifiers, and radio frequency amplifiers. Power semiconductors are found in systems delivering as little as a few tens of milliwatts for a headphone amplifier, up to around a gigawatt in a high voltage direct current transmission line.

Research Example 1

I. INTRODUCTION

Conventional LIGBT forESD protection

Proposed ESD protection devices.

Left - Conventional LIGBT

Right - Proposed ESD protection device

The mechanism of operation of the proposed protection device is as follows. During normal operation of the internal circuit, the ESD protection device does not operate due to the reverse bias between the P-well and the deep N-well. Accordingly, during normal operation of the internal circuit, the ESD protection device does not affect the operation of the internal circuit. However, when an ESD surge injects current into the P+ collector region, punch-through occurs and current is directed towards the emitter due to depletion layer diffusion because of the reverse bias between the P-well and deep N-well. The electrons and holes produced during this process exit via the collector and emitter, respectively. The hole current formed induces a potential buildup across the P-well. When it exceeds the potential barrier between the P-well and the emitter N+, the P-well and emitter N+ are forward biased and the parasitic NPN bipolar transistor formed by the emitter N+, P-well, and deep-N-well is turned on. Since the parasitic NPN bipolar transistor provides the base current for the parasitic PNP bipolar transistor formed by the collector P+, deep N-well and P-well, the result is that the parasitic NPN/PNP bipolar transistors form an ESD current discharge path via positive feedback. Such process is the same for conventional LIGBTs. However, the base current for the parasitic PNP bipolar transistor is increased by the heavily doped N+ floating diffusion region (L1) inside the N-well. Increasing L1 increases the base length of the parasitic PNP bipolar transistor therefore decreasing the current gain and increasing the holding voltage.

II. Process Description & Comparison with Conventional ESD Protection Circuits

TLP characteristics of conventional structures (SCR,GGNMOS and LIGBT).

TLP characteristics of proposed protection device with respect to the L1 parameter

Respect to the L1 parameter of Triggering voltage, Holding voltage and Second Breakdown current.

The proposed protection device was fabricated using the 0.18-um BCD process. The basic electrical characteristics were measured by TLP and are typically presented as a plot of the current versus the voltage (I-V),
showing the turn-on point parameter (Vt1, It1) of the snapback protection structure. In addition, the TLP I-V curve can easily reveal the on-resistance and the second breakdown current. The changes in holding voltage according to the length of the floating N+ diffusion region were measured. In order to further verify the changes in holding voltage due to the reduced current gain of the parasitic PNP bipolar transistor produced from the floating N+ diffusion region, the changes in the holding voltage were measured by increasing the floating N+ diffusion region by varying the base width, which affects the current gain in fixed conditions. Fig. 3 shows the I-V characteristics of the three most common ESD protection devices. Since the SCR has a low holding voltage of 1.5 V, latch-up problems can occur. The GGNMOS has low trigger and holding voltages, therefore, it is not suitable for high-voltage protection. On the other hand, the LIGBT can handle ESD currents effectively by operating two bipolar transistors like the SCR. Moreover, the LIGBT also operates at relatively high voltages and it can be used for higher voltage applications compared to the GGNMOS and the SCR.

III. Electrical Characteristics and Thermal Reliability Measurement Results

The measurement setup for transient latch-up(TLU) test

8 um N+ floating region passes latch-up.

4 um N+ floating region occurs latch-up(fail)

An LIGBT-based ESD protection device was designed and fabricated. The I-V characteristics and ESD robustness of the device were evaluated using TLP and TLU tests. The effect of temperature on trigger and holding voltages was also characterized. In the new ESD protection device, the holding voltage was increased by
inserting a floating N+ diffusion region into the N-well of a conventional LIGBT structure. The results show that
when the length of the floating N+ diffusion region was varied from 4 um, 6 um, and 8 um, the holding voltages
were 8.7 V, 14.7 V and 16.2 V, respectively. It was verified by the TLU test that the device achieves excellent latch-up immunity when the floating N+ diffusion region is 8 um. In addition, the ESD robustness measurements show that the HBM protection level was 8 kV and the MM protection level was 800 V when the floating N+ diffusion region was 4 um and 6 um, while the HBM protection level was 6 kV and the MM protection level was 550 V when the floating N+ diffusion region was 8 um. Therefore, the new LIGBTbased ESD protection device with a floating N+ diffusion region of 8 um can be used for 15 V power IC applications.

Research Example 2

I. INTRODUCTION

The cross-section of conventional IGBT
structure

The cross-section of proposed IGBT structure

Left - Conventional LIGBT

Right - Proposed ESD protection device

The insulated gate bipolar transistors(IGBTs), widely used as high voltage semiconductors to inverters and motor drivers, have better characteristics for high voltage blocking and on-state voltage drop, however, have weak turn-off switching characteristics compared to Power MOSFETs. Also, it is difficult to improve the on-state voltage drop and turnoff switching characteristics simultaneously due to the tradeoff relationship of the two characteristics. The novel designs of IGBTs have been proposed to improve the on-state voltage drop, turn-off switching by using HDE-IGBT, Super Junction and CSTBT etc. These modified structures are necessary for trench process (not necessary planar IGBT’s process). However the trench process is difficult for a design and manufacture than planar IGBT’s DMOS process. Therefore, this paper proposed the novel structure IGBT with inserted n-type MOS using DMOS process. Also, the proposed structure increases injection efficiency of electron current to n-drift region more than conventional structure. The increased injection efficiency has shown the improved electrical characteristics.

II. Process Description & Comparison with Conventional ESD Protection Circuits

Latch-up characteristics of the conventional and proposed IGBT (@gate bias=15V)

The electron and hole mobility of accumulation
layer of conventional and proposed

Fig.5.The hole current component flowing into the Pbase region under N+ emitter of conventional and proposed

shows the conventional and proposed structures of IGBT. The proposed structure has n-type MOSFET between adjacent cells to reduce the conduction loss and turn-off time as well as static latch-up susceptibility. The highly doped P+ and N++ area of n-type MOS structure in the proposed IGBT can be made with the process of forming an emitter P+ and N++ area of the conventional IGBT without additional mask. And the general operating mechanism of the proposed IGBT is the same to that of the conventional IGBT, which is, the injection of highdensity holes from the P+ collector into the N-drift region and electron current from N+ emitter into the N-drift. However, the injected electron current density of the proposed IGBT is much better than that of conventional IGBT because of the increased area of the n-type MOS and n-well. And the increased electron current by the incorporated MOSFET enhances the mobility of electron and holes that led to decrease of on-state voltage drop. Also, the proposed IGBT has a wide latch-up limit and shorter turn-off time because the P+ area in the MOSFET operates like diverter

III. Electrical Characteristics and Thermal Reliability Measurement Results

Forward blocking characteristics of the conventional and proposed IGBT

Turn-off characteristics of the conventional IGBT
and proposed IGBT

The novel 2.5kv IGBT incorporating an n-type MOSFET with the aim of the improving the trade-off relation between switching time and conduction loss is proposed. The incorporated nMOSFET between two adjacent cells provides an additional current path that led to the alleviation of the current and field crowding effect. Also, the structure led to the increase of collector current of IGBT and the decrease of the onstate voltage drop. Then, the turn-off time and the static latch-up susceptibility are decreased because of the p+ region of the incorporated MOSFET of the proposed IGBT. In the experimental results, the turnoff time and on state voltage drop are decreased by approximately 8% and 15% respectively, compared to a conventional IGBT (Turn-off time : 6.2us, on-state voltage drop: 3.34V). And the proposed IGBT provides higher latching current of 429 A / cm2 than conventional IGBT (308A/cm2).