RESEARCH

ESD PROTECTION CIRCUIT

  • Electrostatic discharge (ESD) is the sudden flow of electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown. A buildup of static electricity can be caused by tribocharging or by electrostatic induction. The ESD occurs when differently-charged objects are brought close together or when the dielectric between them breaks down, often creating a visible spark. ESD can create spectacular electric sparks (lightning, with the accompanying sound of thunder, is a large-scale ESD event), but also less dramatic forms which may be neither seen nor heard, yet still be large enough to cause damage to sensitive electronic devices. Electric sparks require a field strength above approximately 40 kV/cm in air, as notably occurs in lightning strikes. Other forms of ESD include corona discharge from sharp electrodes and brush discharge from blunt electrodes. ESD can cause harmful effects of importance in industry, including explosions in gas, fuel vapor and coal dust, as well as failure of solid state electronics components such as integrated circuits. These can suffer permanent damage when subjected to high voltages. Electronics manufacturers therefore establish electrostatic protective areas free of static, using measures to prevent charging, such as avoiding highly charging materials and measures to remove static such as grounding human workers, providing antistatic devices, and controlling humidity. ESD simulators may be used to test electronic devices, for example with a human body model or a charged device model.

  •  Research Example 1

I. A New Dual-Directional SCR

Structure of (a) low-triggering DDSCR (LTDDSCR) and (b) proposed ESD protection circuit

IV characteristics of the structures of SCR structures and the Proposed ESD protection device

  • The structures of the conventional LTDDSCR and the proposed ESD protection device are shown in Figure shows their equivalent circuits. As a DDSCR structure is symmetrical, it provides the same ESD surge path for both positive and negative ESD surges. Typical LTDDSCRs help lower the avalanche breakdown and reduce the trigger voltage by forming an additional P+ bridge region between the well regions. When a positive ESD is applied to terminal A, an ESD surge path is formed through the latch-mode of the two parasitic bipolar transistors (Qnpn1 and Qpnp). The proposed ESD protection device uses two PMOS structures to minimize the base region of the PNP parasitic bipolar transistor through a gate, giving it a relatively short discharge path. When a positive ESD surge is applied to terminal A, an avalanche breakdown occurs in the left N-well region/P+ bridge region, and the potential of the middle P region increases. If the increase in the voltage is sufficient, the forward junction of the right P+ bridge region/N-well region is turned on, and the parasitic bipolar transistor (Q1, Q2, Q3, Q5) is also turned on as a structural characteristic, thereby forming an ESD surge path.

II. The Operation Principles of The Proposed Structure

Equivalent circuit of (a) DDSCR, LTDDSCR and  (b)the  proposed ESD protection circuit

Layout for the VDD-VSS pin (DS) and I/O pins with four types of ESD (PD, ND, PS, and NS)

A layout with design variables of the proposed ESD protection circuit

  • uThe proposed design variable D1 represents the length of the two proposed bridge regions the use of this variable is a conventional method of increasing the holding voltage of SCR-based ESD protection devices. The base region of the NPN parasitic bipolar transistor is adjusted to increase the holding voltage. Unfortunately, this method of increasing the base region of an NPN parasitic bipolar transistor has drawbacks in terms of area expansion and significantly reduces the durability. This method increases the high concentration region. Thus, the resistance of the protection circuit is increased by reducing the current driving capability of the PNP parasitic bipolar transistors as the emitter of the PNP parasitic bipolar transistors increases. On the other hand, the design variable L represents the length of the two gates. The proposed ESD protection device can simultaneously increase the lengths of all the effective base regions of the operating PNP parasitic transistors (Q1, Q2, Q3, Q4), thus effectively increasing the holding voltage with a relatively low on-state resistance and a high effective robustness.

III. Results and Discussion

TLP I-V characteristic curves of traditional DDSCR, LTDDSCR and the proposed ESD protection circuit

When positive ESD serge is applied to terminal A, TLP I-V characteristic curves of the proposed ESD protection circuit according to changes in (a) D1 design and (b) L variables

Electrical characteristic  at high temperature (300 to 500 K) second breakdown current and effectiveness robustness

  • In this paper, we propose a novel DDSCR with a higher holding voltage and a better ESD tolerance than conventional low-triggering DDSCRs (LTDDSCRs), realized by operating two additional parasitic bipolar transistors. The proposed ESD protection device was developed through a 0.18 µm CMOS process, and a timeline pulse system was used to verify its properties. The measurement results show that the proposed ESD protection device exhibits an improved tolerance and a high holding voltage and is expected to be reliable in 5 V-class applications

  •  Research Example 2

I. Device Structure and Description

Structures with equivalent circuit diagrams of (a) Low-Voltage- Triggering SCR(LVTSCR), (b) Low -Ron SCR(LRSCR), (c) The proposed ESD protection device

Cross sections of (a) LVTSCR, (b) LRSCR and (c) The proposed ESD protection device with net doping concentration and mesh

Impact ionization of (a) LVTSCR, (b) LRSCR and (c) The proposed ESD protection device

  • Research to improve the current drive capability of the ESD protection circuit is crucial for increasing the area efficiency Moreover, because ESD has negative and positive polarities, the reverse direction characteristic, as well as the forward direction characteristic of the ESD protection circuit, is particularly important. However, SCR-based ESD protection devices have 

the disadvantage of operating with only one diode for negative pulses. Therefore, in this paper, a new SCR structure with double triggering operation utilizing an additional high-beta parasitic NPN bipolar transistor with improved current driving ability, triggering characteristics, and reverse characteristics is proposed with design parameters for the holding voltage.

II. The ESD Protection Mechanism of the Proposed Device

(a) Mix-mode simulation circuit for HBM 4kV pulse and the simulated waveform for (b) LVTSCR, (c) LRSCR and (d) the proposed ESD protection device.

(a) Design variables with doping concentration and DC-IV simulation curves in simulation (b) Increased L1 by 1um, (c) Increased L2 by 1um, (d) Both L1 and L2 increase by 0.5um simultaneously

Total current-flow-line of (a) LVTSCR,

(b) LRSCR and (C) the proposed

  • The proposed ESD protection device has high tolerance characteristics owing to its high current driving capability(Fig. 4, Fig. 5) and the proposed device 

can simultaneously increase the design variables L1 and L2 to increase the effective base length of all parasitic bipolar transistors (Qp3, Qn2, Qn3) and effectively optimize the holding voltage without increasing the thin oxide region. Moreover, the increase in trigger voltage can be made small.

III. Results and Discussion

When positive(left) and negative(right) ESD Serge is applied to anode, TLP I-V characteristic curves of conventional LVTSCR, LRSCR and the proposed

TLP I-V characteristic curves of the proposed ESD protection circuit according to changes in L1(left) and (b) segment(right)

  • In this paper, a SCR structure with a high current drive capability and improved tolerance characteristics was proposed. This provides a parallel discharge path that greatly reduces the on-resistance component in the ESD state. The improved electrical characteristics of the proposed ESD protection circuit were verified by comparing it with LVTSCR and LRSCR by TLP measurements. A high-temperature measurement test using a hot-chuck control system verified that the proposed ESD protection circuit has excellent thermal reliability with a low ON-resistance component. The proposed ESD protection device was fabricated using the 0.18 μm BCD process contributing to cost reduction and reliability improvement due to increased area efficiency when it is used for 5 V or similar applications

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